The present invention relates to analog to digital converters and more specifically to dual ramp integrating analog to digital converters.
There are many types of analog to digital (A/D) converters. Integrating A/D converters are one type of A/D converter known in the art. Integrating A/D converters integrate unknown and fixed charges over fixed and measured time periods respectively.
Dual ramp integrating A/D converters are one known type of integrating A/D converters. The typical dual ramp integrating converter integrates the signal being measured for a fixed period of time onto a capacitor and then de-integrates the capacitor charge back to the starting voltage using a reference voltage as the input. The converter measures the time it takes to return to the starting voltage. The resulting digital conversion in the time counter or digital accumulator is then proportional to the ratio of the unknown and reference signals.
One problem with this type of A/D converter is that the integration signal must be constrained so as not to cause the integration capacitor and associated analog circuitry to saturate. This limits the dynamic range of the integration state.
A second problem with this type of converter is the defined boundary between the integration of the input signal and the conversion of that signal into a digital value. The need to perform de-integration introduces latency in the delivery of the digital information. This latency typically increases as the number of bits of A/D resolution increases.
In view of the foregoing it would be desirable to have a dual slope integrating A/D converter that avoids the above-described problems associated with saturation of the integration signal and which additionally reduces the conversion latency.